1. Field of the Invention
The present invention relates to digital computer memories. More specifically, the present invention is directed to a digital computer memory having a plurality of digital data output paths.
2. Description of the Prior Art
All digital computer architectures are based around an array of data storage registers and an arithmetic logic unit (ALU). Data handling operations are performed by accessing data from the storage registers, supplying this data to the ALU where a predetermined operation is performed on the data by a central processing unit (CPU) and writing the resultant modified data back into one of the registers. In the prior art, these arrays of data registers have been implemented by individual flip-flops, small "scratch pad" memories, random access memories, etc. A conventional memory array used as a data storage register storage slows down the operation of the central processing unit (CPU) because, while the CPU can only access one internal location in the memory array at a time, most CPU operations such as addition, subtraction, etc. require two pieces of data for their execution. This type of operation then requires two internal memory operation time intervals in retrieve the two pieces of stored data, or operands. Similarly, during the "write" operation to store the result of the CPU operation, an internal memory time interval is required for the memory array to function as a data storage register.